VHDL Lab Exercises
MSc Course: “Design of Digital Systems with VHDL” (Lab Exercises)
MSc Title: “Electronics & Information Processing” @ University of Patras, Greece
Author: Dimos Katsimardos
Period: 2015 November - 2016 February
Description: VHDL lab exercises from simple behavioral and sequential circuits to a simple CPU design with hardwired and microprogrammed logic
Software/CAD: Altera Quartus 7.2
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Simple Combinational Circuits
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Advanced Combinational Circuits
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Sequential Circuits
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Serial Adders/Subtractors
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Arithmetic & Logic Unit ( ALU )
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Up Down Presetable Counter - Universal Shift Register - Combinational Shift Circuit
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A very simple CPU